1. Field of the Invention
The present invention relates generally to methods for forming patterned conductor layers separated by patterned dielectric layers within microelectronics fabrications. More particularly, the present invention relates to dual damascene methods for forming patterned conductor layers separated by patterned dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and patterned conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor interconnect layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. Such patterned microelectronics conductor interconnect layers often access within the microelectronics fabrications within which they are formed patterned conductor contact stud layers or patterned conductor interconnect stud layers. For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 9.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers which assist in providing microelectronics fabrications exhibiting enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance, and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, fluorinated polyimide organic polymer spin-on-polymer dielectric materials, poly-arylene-ether organic polymer spin-on-polymer dielectric materials and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesqiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials, and carbon bonded fluorocarbon silsesquioxane spin- on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming patterned low dielectric constant microelectronics dielectric layers interposed between the patterns of patterned conductor interconnect layers which access patterned conductor stud layers within microelectronics fabrications, such microelectronics fabrication structures are often not formed entirely without problems. In particular, such microelectronics fabrication structures are typically formed employing an etch stop layer formed interposed between: (1) a patterned first dielectric layer through which is formed a patterned conductor stud layer; and (2) a patterned low dielectric constant dielectric layer which is formed adjoining the patterned conductor interconnect layer which contacts the patterned conductor stud layer. The etch stop layer typically assures optimal definition of the patterned conductor interconnect layer within respect to the patterned conductor stud layer. Unfortunately, the presence of such etch stop layers often provides additional microelectronics fabrication complexity within microelectronics fabrications within which are formed patterned conductor interconnect layers which contact patterned conductor stud layers. Similarly, even with the presence of such etch stop layers, it is often difficult to form both patterned conductor interconnect layers and contiguous patterned conductor stud layers with enhanced linewidth control.
It is thus towards the goal of forming microelectronics fabrication structures comprising patterned low dielectric constant dielectric layers separating patterned conductor interconnect layers which in turn contact patterned conductor stud layers, with enhanced linewidth control, that the present invention is specifically directed. In a more general sense, the present invention is also directed towards forming within microelectronics fabrications patterned conductor interconnect layers contiguous with patterned conductor stud layers, with enhanced linewidth control, where neither the patterned conductor interconnect layers nor the patterned conductor stud layers are necessarily separated by low dielectric constant dielectric layers.
Various methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, several ion implant assisted methods have been disclosed within the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications. Examples of such methods are disclosed by: (1) Taylor et al., in U.S. Pat. No. 4,377,437 (ion implant method where ion implanted portions of a substrate layer react with a reactant within a reactant atmosphere to form a protective compound within the ion implanted portions of the substrate layer, which ion implanted portions are inhibited from further etching within the reactant atmosphere); (2) Taji et al., in U.S. Pat. No. 4,634,494 (ion implant method employing boron ions implanted into a phosphosilicate glass layer to selectively modify the etch properties of the boron doped phosphosilicate glass layer so formed); (3) Jain et al., in U.S. Pat. No. 4,652,334 (ion implant method which facilitates selective etching of ion implanted portions of a silicon oxide layer within an ammoniacal hydrogen peroxide etchant); (4) Reichert et al., in U.S. Pat. No. 4,863,556 (ion implant method which facilitates selective etching of ion implanted portions of a silicon oxide layer and an underlying silicon nitride layer within a phosphoric acid etchant); and (5) Tsuhchiaki, in U.S. Pat. No. 5,444,007 (ion implant method for simultaneously forming narrow trenches with straight sidewalls and wide trenches with tapered sidewall profiles within substrates).
In addition, Moslehi, in U.S. Pat. No. 5,460,693, discloses a fully dry microlithography method for forming a patterned processable layer within a microelectronics fabrication, where the fully dry microlithography method is predicated upon photosensitive properties of a halogen doped layer employed as a mask layer within the fully dry microlithography method.
Further, Cheung et al., in U.S. Pat. No. 5,550,405, discloses a lift off method employing a tri-layer resist layer for forming an interconnect structure employing a low resistance metal layer separated by a low dielectric constant dielectric layer within a microelectronics fabrication. Within the method, a low dielectric constant dielectric material employed within the low dielectric constant dielectric layer is employed as a diffusion barrier to diffusion of a low resistance metal employed within the low resistance metal layer.
Finally, there is also disclosed in the art several damascene and dual damascene methods for forming patterned conductor interconnect layers, optionally contiguous with patterned conductor stud layers, within microelectronics fabrications. Examples of such methods are disclosed by: (1) Fiordalice et al., U.S. Pat. No. 5,578,523 (damascene method employing an aluminum nitride polish assisting layer to attenuate dishing or cusping of a chemical mechanical polish (CMP) planarized conductor interconnect layer formed employing the damascene method); (2) Zheng et al., in U.S. Pat. No. 5,602,053 (dual damascene method incorporating an antifuse structure within a dual damascene structure); (3) Mu et al., in U.S. Pat. No. 5,612,254 (damascene method for forming a patterned conductor interconnect layer contacting a patterned conductor stud layer within a microelectronics fabrication); (4) Huang et al., in U.S. Pat. No. 5,635,423 (modified dual damascene method employing an etch stop layer interposed between a first dielectric layer through which is formed a patterned conductor stud layer and a second dielectric layer through which is formed a patterned conductor interconnect layer); (5) Dennison et al., in U.S. Pat. No. 5,651,855 (dual damascene method employing a single dielectric layer with two separate masking and etching process steps); (6) Avanzino et al., in U.S. Pat. No. 5,686,354 (dual damascene method employing a single dielectric layer and a conformal trench masking layer); (7) Avanzino et al., in U.S. Pat. No. 5,705,430 (dual damascene method employing two dielectric layers and sacrificial via fill layer); and (8) Avanzino et al., in U.S. Pat. No. 5,614,765 (a dual damascene method where a conductor stud layer is formed in a via formed in a self aligned fashion through a dielectric layer).
Desirable within the art of microelectronics fabrication are methods which may be employed to form within microelectronics fabrications patterned conductor interconnect layers contiguous with patterned conductor stud layers, with enhanced linewidth control. More particularly desirable in the art of microelectronics fabrication are methods which may be employed to form within microelectronics fabrications low dielectric constant dielectric layers interposed between the patterns of patterned conductor interconnect layers which in turn contact patterned conductor stud layers, with enhanced linewidth control.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.